There are many types of applications in the data processing area in which a plurality of processors operate in parallel to execute a single job or solve a single problem. One such area is that of hardware accelerators which are used to solve a variety of computer aided design problems. In designing such a system, it was decided to use a relatively large number of commercially available microprocessors that would operate in parallel under the control of a single executive processor. By way of example, it was decided to use sixteen microprocessors and allow for the expansion of the system to accommodate even more. To reduce bus contention and bottlenecks, which would occur if all the processors were connected to a single bus, several busses are connected into a hierarchy. The executive processor is connected to a global bus which in turn is connected to a plurality of cell busses. Each cell bus is connected to plural processors.
Next, it was decided that communication between the different processors would be handled primarily through an interrupt mechanism in which each processor would be given a unique interrupt. However, the standard bus design for such processors has a limited number of prioritized interrupt lines so that where the number of processors exceeds the number of interrupt lines, each processor cannot be given a unique interrupt by being connected to a different line. One solution would be to connect plural processors in a daisy chain, as with conventional I/O devices, but such a solution would create a bottleneck where plural processors in a given daisy chain simultaneously require being interrupted. Another solution would be to change the bus protocol and add a different line for each processor. Again such a solution would increase the cost of the system. Thus, a novel interrupt mechanism described hereinafter, was designed enabling each processor to have a unique interrupt without requiring modification of a conventional bus protocol.